TTTC's Electronic Broadcasting Service
TTTC's Electronic Broadcasting Service

3rd International Verification and Security Workshop
(IVSW)
July 2-4, 2018
Hotel Cap Roig, Platja d’Aro, Costa Brava, Spain

http://tima.univ-grenoble-alpes.fr/conferences/ivsw/ivsw18/

IVSW 2018 - CALL FOR PAPERS

Scope

Issues related to verification and security are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in quality, reliability and security needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective verification techniques and security solutions. These needs have increased dramatically with the increased complexity of complex electronic systems and the fast adoption of these systems in all aspects of our daily lives. The goal of IVSW is to bring industry practitioners and researchers from the fields of security, verification, validation, test, and reliability to exchange innovative ideas and to develop new methodologies for solving the difficult challenges facing us today in various SoC design environments. IVSW 2018 is sponsored by IEEE Council on Electronic Design Automation (CEDA).

Submissions

Authors are invited to submit papers or abstracts in the above technical areas. All submissions must be done electronically following the instructions at the workshop web site. IVSW formal Proceedings will get published by IEEE Xplore after the workshop. Inclusions in the formal proceedings is optional. There is a 6-page limit for each paper. Additional pages can be included for an extra fee. Papers should be in the standard IEEE conferences double-column format. At least one author of each accepted paper must attend and register for the workshop to present the paper.

The workshop seeks submissions from academia and industry presenting novel research results on the following topics of interest:

  • Verification challenges of IoT
  • High-level test generation for functional verification
  • Emulation techniques and FPGA prototyping
  • Triage and debug methodologies
  • Silicon debugging
  • Low-power verification
  • Formal techniques and their applications
  • Verification coverage
  • Performance validation and characterization
  • Design for Verifiability (DFV)
  • Memory and coherency verification
  • ESL design and Virtual Platforms
  • Design for security and security validation
  • CAD metrics and tools for security
  • Cryptography and trusted computing
  • Detection of Trojans and counterfeit electronics
  • Methods for IP protection (obfuscation, encryption, etc.)
  • Fault-based side-channel attacks and countermeasures
  • Hardware security primitives design and evaluation
  • Security for analog/mixed signal (AMS) circuits
  • Security in automotive, railway, avionics, space, Internet of Things (IoT)
  • Data analytics in verification and security
  • Cross layer security and verification
  • Security of design environment and tools, and supply chain

Special Sessions, Panels and Tutorials:  Proposals for special sessions, panels and tutorials are also invited.  Please submit the abstract of your proposal electronically as early as possible before the deadline.

Key Dates

Submission deadline: Feb 21, 2018

Notification of acceptance: Apr 4, 2018

Camera-ready papers due: May 7, 2018    

Additional Information

Federative Event on Design for Robustness (FEDfRo):  IVSW’18 is held as part of the 3rd Federative Event on Design for Robustness (FEDfRo). IVSW will be co-located with three successful conferences: the Int’l On-line Test Symposium (IOLTS), The Int’l symposium on power and timing (PATMOS), and the Int’l Mixed Signal Test Workshop (IMSTW). This will be an ideal environment for cross-examination of security, verification, test, timing, power, reliability experiences and innovative solutions. Registered attendees of any of the three events will be allowed to attend the technical sessions of the other two. The plenary session and social activities of the three events will be held jointly. For all details about this federated event see: http://tima.univ-grenoble-alpes.fr/conferences/fedfro/

About the Location:  IVSW 2018 will be held at Hotel Cap Roig, Platja d’Aro, Costa Brava, Spain. The hotel is right on the Mediterranean in one of the most admired corners of Costa Brava for the clear and transparent waters offered by its beaches. It is also notable for its gastronomy, its popular walking routes and its spectacular views. The hotel is about one hour by car north east of Barcelona.

 

Questions:  Contact General Chair: magdy.abadir@gmail.com or Program Co-Chair Ilia Polian ilia.polian@informatik.uni-stuttgart.de


For more information, visit us on the web at: http://tima.univ-grenoble-alpes.fr/conferences/ivsw/ivsw18/

The 3rd International Verification and Security Workshop is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Council on Electronic Design Automation (CEDA).


IEEE Computer Society-Test Technology Technical Council

TTTC CHAIR
Chen-Huan CHIANG
Intel - USA
E-mail chen-huan.chiang@intel.com

PAST CHAIR
Michael NICOLAIDIS
TIMA laboratory - France
E-mail michael.nicolaidis@imag.fr

TTTC 1ST VICE CHAIR
Matteo SONZA REORDA
Politecnico di Torino - Italy
E-mail matteo.sonzareorda@polito.it

SECRETARY
Joan FIGUERAS
Un. Politec. de Catalunya - Spain
E-mail figueras@eel.upc.es

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Paolo BERNARDI

Politecnico di Torino
- Italy
E-mail paolo.bernardi@polito.it

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
E-mail rkapur@synopsys.com

EUROPE
Giorgio DI NATALE
LIRMM - France
E-mail giorgio.dinatale@lirmm.fr

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Giorgio DI NATALE
LIRMM - France
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
Adith SINGH
Auburn University – USA
E-mail adsingh@eng.auburn.edu

TTTC 2ND VICE CHAIR
Rohit KAPUR
Synopsys, Inc. – USA
E-mail rkapur@synopsys.com

FINANCE
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com


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